What is considered for a prospective technique for improving the bit density of nonvolatile semiconductor memory devices such as NAND type flash memories is stacking of memory cells because miniaturizing techniques have almost come to their limit. As one example of the stacking technique, a stacked NAND type flash memory using memory transistors configured by vertical transistors is proposed. A stacked NAND type flash memory includes memory strings each configured by a plurality of memory transistors connected in series in the stacking direction, and select transistors provided at both ends of each memory string.
As has been conventionally required, simplification of the manufacturing process is required also for this stacked NAND type flash memory, in order to save the manufacturing cost. However, the simplification of the manufacturing process requires that the gates of memory transistors included in a plurality of memory strings be connected commonly to one word line WL. Therefore, an erasing operation of erasing data in the memory transistors can only be executed simultaneously on the basis of all the memory strings connected by one word line WL (i.e., on a block basis).